The present invention relates to a semiconductor device and a method of fabricating the same.
Semiconductor memories such as DRAMs are more and more down-scaled in recent years. 1T-1C (1 Transistor-1 Capacitor) type DRAM, however, needs a certain area for the capacitor to ensure a storage capacitance of the capacitor. This limits the degree of down-scaling of the 1T-1C DRAM.
Also, since a capacitor must be formed in the 1T-1C DRAM, the fabrication process complicates, and the cost increases.
To solve these problems, a technique which forms a DRAM on an SOI (Silicon On Insulator) substrate is developed. For example, patent reference 1 or 2 (to be described later) discloses a DRAM formed by using an FBC (Floating Body Cell). The FBC is a memory cell formed by one transistor by using an SOI substrate.
This FBC is formed as a MOS transistor on an SOI substrate. A source region, drain region, and body region are formed in an SOI layer. The body region sandwiched between the source and drain regions is electrically floating, and data can be stored by charging or discharging this region.
In the FBC as described above, the data holding time prolongs and the yield increases as the capacitance between the body region and a fixed-potential element such as a support substrate increases.
In an FBC shown in FIG. 32 of patent reference 1, the capacitance between the body region and the support substrate is increased by using an SOI substrate having a thin buried oxide film (to be referred to as a BOX layer hereinafter).
On the other hand, in an FBC shown in FIG. 25 of patent reference 1, a back gate electrode is formed in a thick BOX layer to increase the capacitance between the body region and this back gate electrode.
Unfortunately, even when these structures are used, it is difficult to form an FBC having a sufficiently long data holding time and high yield.
References disclosing the conventional semiconductor memories are as follows.
1: Japanese Patent Laid-Open No. 2002-246571
2: Japanese Patent Laid-Open No. 2002-343886